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(R)
DALC208SC6
LOW CAPACITANCE DIODE ARRAY
Application Specific Discretes A.S.D.TM
MAIN APPLICATIONS Where ESD and/or over and undershoot protection for datalines is required : Sensitive logic input protection Microprocessor based equipment Audio / Video inputs Portable electronics Networks ISDN equipment USB interface DESCRIPTION The DALC208SC6 diode array is designed to protect components which are connected to data and transmission lines from overvoltages caused by electrostatic discharge (ESD) or other transients. It is a rail-to-rail protection device also suited for overshoot and undershoot suppression on sensitive logic inputs. The low capacitance of the DALC208SC6 prevents from significant signal distortion. FEATURES PROTECTION OF 4 LINES PEAK REVERSE VOLTAGE: VRRM = 9 V per diode VERY LOW CAPACITANCE PER DIODE: C < 5 pF VERY LOW LEAKAGE CURRENT: IR < 1 A BENEFITS Cost-effectiveness compared to discrete solution High efficiency in ESD suppression No significant signal distortion thanks to very low capacitance High reliability offered by monolithic integration Lower PCB area consumption versus discrete solution
1
SOT23-6L (SC74)
FUNCTIONAL DIAGRAM
I/O 1
I/O 4
REF 2
REF 1
I/O 2
I/O 3
COMPLIES WITH THE FOLLOWING STANDARDS : IEC 1000-4-2 level 4 MIL STD 883C - Method 3015-6 (human body test) class 3
February 1999 - Ed: 3A
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DALC208SC6
ABSOLUTE MAXIMUM RATINGS (Tamb = 25C). Symbol VPP VRRM VREF VIn max. VIn min. IF IFRM IFSM Parameter IEC1000-4-2, air discharge IEC1000-4-2, contact discharge Peak reverse voltage per diode Reference voltage gap between VREF2 and VREF1 Maximum operating signal input voltage Minimum operating signal input voltage Continuous forward current (single diode loaded) Repetitive peak forward current (tp = 5 s, F = 50 kHz) Surge non repetitive forward current rectangular waveform (see curve on figure 1) tp = 2.5 s tp = 1 ms tp = 100 ms Storage temperature range Maximum junction temperature Value 15 8 9 9 VREF2 VREF1 200 700 Unit kV V V V V mA mA
6 2 1 -55 to + 150 150
A
Tstg Tj
C C
THERMAL RESISTANCE Symbol Rth(j-a) Junction to ambient (note 1) Parameter Value 500 Unit C/W
Note 1: device mounted on FR4 PCB with recommended footprint dimensions.
ELECTRICAL CHARACTERISTICS (Tamb = 25C). Symbol VF IR C Parameter Forward voltage Reverse leakage current per diode Input capacitance between Line and GND Conditions IF = 50 mA VR = 5 V see note 3 7 Typ. Max. 1.2 1 Unit V A pF
Note 2: The dynamical behavior is described in the Technical Information section, on page 4.
Note 3: Input capacitance measurement
REF2
I/O VR G
+V CC
REF1 connected to GND REF2 connected to +Vcc Input applied : Vcc = 5V, Vsign = 30 mV, F = 1 MHz
REF1
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DALC208SC6
Fig. 1: Maximum non-repetitive peak forward current versus rectangular pulse duration (Tj initial = 25C).
IFSM(A) 8 7 6 5 4 3 2 1 0 0.001 0.01 0.1 1 tp(ms) 10 100 1000
I/O vs REF1 or REF2
I/O vs REF1 or REF2
Fig. 2: Reverse clamping voltage versus peak pulse current (Tj initial = 25C), typical values. Rectangular waveform tp = 2.5 s.
Ipp(A) 2.0
tp=2.5s
1.0
0.1
5
10
15 Vcl(V)
20
25
30
Fig. 3: Variation of leakage current versus junction temperature (typical values).
IR(A) 100
Fig. 4: Input capacitance versus reverse applied voltage (typical values).
C(pF) 8.0 7.5
10
7.0
1
6.5 6.0
0.1
5.5
0.01 25 50 75 Tj(C) 100 125 150
F=1MHz Vsign=30mV Vref1/ref2=5V
5.0
0
1
2 VR(V)
3
4
5
Fig. 5: Peak forward voltage drop versus peak forward current (typical values). Rectangular waveform tp = 2.5 s.
IFM(A) 10.0
Tj=25C Tj=150C
1.0
I/O vs REF 1 or REF2
0.1
0
2
4
6
8
10 12 VFM(V)
14
16
18
20
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DALC208SC6
TECHNICAL INFORMATION SURGE PROTECTION The DALC208SC6 is particularly optimized to perform surge protection based on the rail to rail topology. The clamping voltage VCL can be calculated as follow : VCL+ = VREF2 + VF VCL- = VREF1 - VF for positive surges for negative surges APPLICATION EXAMPLE If we consider that the connections from the pin REF2 to VCC and from REF1 to GND are done by two tracks of 10mm long and 0.5mm large; we assume that the parasitic inductances of these tracks are about 6nH. So when an IEC 1000-4-2 surge occurs, due to the rise time of this spike (tr=1ns), the voltage VCL has an extra value equal to Lw.dI/dt. The dI/dt is calculated as: di/dt = Ip/tr 24 A/ns The overvoltage due to the parasitic inductances is: Lw.di/dt = 6 x 24 144V By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping voltage will be : VCL+ = +23 + 144 167V VCL- = -18 - 144 -162V We can reduce as much as possible these phenomena with simple layout optimization. It's the reason why some recommendations have to be followed (see paragraph "How to ensure a good ESD protection").
with : VF = Vt + rd.Ip (VF forward drop voltage) / (Vt forward drop threshold voltage) According to the curve Fig.5 on page 3, we assume that the value of the dynamic resistance of the clamping diode is typically rd = 0.7 and Vt = 1.2V. For an IEC 1000-4-2 surge Level 4 (Contact Discharge: Vg=8kV, Rg=330), VREF2 = +5V, VREF1 = 0V, and if in first approximation, we assume that : Ip=Vg/Rg 24A. So, we find: VCL+ +23V VCL- -18V Note: the calculations do not take into account phenomena due to parasitic inductances
Fig. A1: ESD behavior; parasitic phenomena due to unsuitable layout.
Lw REF2=+Vcc Vf I/O Lw di dt
ESD SURGE
di Vcl+ = Vcc+Vf+ Lw dt surge >0 VI/O Lw di dt Vcl- = -Vf- Lw di dt surge <0
REF1=GND
tr=1ns
Vcl+ 167V
t
-Vf POSITIVE SURGE -Lw di dt NEGATIVE SURGE
Lw di dt Vcc+Vf
t tr=1ns
-162V Vcl-
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DALC208SC6
HOW TO ENSURE A GOOD ESD PROTECTION While the DALC208SC6 provides a high immunity to ESD surge, an efficient protection depends on the layout of the board. In the same way, with the rail to rail topology, the track from the VREF2 pin to the power supply +VCC and from the VREF1 pin to GND must be as short as possible to avoid overvoltages due to parasitic phenomena (see Fig. A1). It's often harder to connect the power supply near to the DALC208SC6 unlike the ground thanks to the ground plane that allows a short connection. To ensure the same efficiency for positive surges when the connections can't be short enough, we recommend to put close to the DALC208SC6, between VREF2 and ground, a capacitance of 100nF to prevent from these kinds of overvoltage disturbances (see Fig. A2). The add of this capacitance will allow a better protection by providing during surge a constant voltage. Fig. A3, A4a and A4b show the improvement of the ESD protection according to the recommendations described above. Fig. A3: ESD behavior: measurements conditions (with coupling capacitance).
ESD SURGE
TEST BOARD
DALC 208
+5V
Fig. A4a: Remaining voltage after the DALC208SC6 during positive ESD surge.
IEC 1000-4-2 Air Discharge (150pF/330 ) Vpp=15kV
Fig. A2: ESD behavior: optimized layout and add of a capacitance of 100nF.
ESD SURGE Lw
REF2=+Vcc
C=100nF
I/O Vcl+ = Vcc+Vf VI/O Vcl- = -Vf surge >0 surge <0
REF1=GND
Fig. A4b: Remaining voltage after the DALC208SC6 during negative ESD surge.
Vcl+
t
POSITIVE SURGE
NEGATIVE SURGE
t
Vcl-
Important: A main precaution to take is to put the protection device closer to the disturbance source (generally the connector).
Note: The measurements have been done with the DALC208SC6 in open circuit.
IEC 1000-4-2 Air Discharge (150pF/330 ) Vpp=15kV
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DALC208SC6
CROSSTALK BEHAVIOR 1- Crosstalk phenomena Fig. A4: Crosstalk phenomena.
RG1 Line 1 1VG1 + 12VG2
VG1 RG2 Line 2
RL1
VG2
RL2
2VG2 + 21VG1
DRIVERS
RECEIVERS
The crosstalk phenomena are due to the coupling between 2 lines. The coupling factor (12 or 21) increases when the gap across lines decreases, particularly in silicon dice. In the example above the expected signal on load RL2 is 2VG2, in fact the real voltage at this point has got an extra value 21VG1. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few k). The following chapters give the value of both digital and analog crosstalk. 2- Digital Crosstalk Fig. A5: Digital crosstalk measurements.
+5V 74HC04 Line 1 +5V VG1 Line 2 21 VG1 +5V +5V
100nF
Fig. A6: Digital crosstalk results.
74HC04
Square Pulse Generator 5KHz
DALC208SC6
Figure A5 shows the measurement circuit used to quantify the crosstalk effect in a classical digital application. Figure A6 shows that in such a condition: signal from 0V to 5V and a rise time of 5 ns, the impact on the disturbed line is less than 100mV peak to peak. No data disturbance was noted on the concerned line. The same results were obtained with falling edges.
Note: The measurements have been done in the worst case i.e. on two adjacent cells (I/O1 & I/O4).
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DALC208SC6
3- Analog Crosstalk Fig. A7: Analog crosstalk measurements.
TRACKING GENERATOR TEST BOARD SPECTRUM ANALYSER
50
DALC 208
+5V
Vg
50 Vin
C=100nF
Vout
Figure A7 gives the measurement circuit for the analog application. In usual frequency range of analog signals (up to 100MHz) the effect on disturbed line is less than -45 dBm (please see Fig. A8). Fig. A8: Analog crosstalk results.
dBm 0 -20
+5V
Fig. A9: Measurement conditions.
TRACKING GENERATOR
TEST BOARD
SPECTRUM ANALYSER
50
DALC 208
Vg
50 Vin
C=100nF
-40 -60 -80 -100
Vout
Fig. A10: DALC206SC6 attenuation.
1 10 f(MHz) 100 1,000
dBm 0
As the DALC208SC6 is designed to protect high speed data lines, it must ensure a good transmission of operating signals. The attenuation curve give such an information. Fig. A10 shows that the DALC208SC6 is well suitable for data line transmission up to 100 Mbit/s while it works as a filter for undesirable signals as GSM (900MHz).
-10
-20
-30
1
10 f(MHz)
100
1,000
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DALC208SC6
APPLICATION EXAMPLES Video line protection
Pin N Signal RED VIDEO GREEN VIDEO or COMPOSITE SYNC with GREEN VIDEO BLUE VIDEO GROUND DDC (Display Data Channel) GROUND RED GROUND GREEN GROUND BLUE GROUND NC SYNC GROUND GROUND SDA (Serial Data) HORIZONTAL SYNC or COMPOSITE SYNC VERTICAL SYNC (VCLK) SCL (Serial Clock)
+Vcc 100nF
DALC 208
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
5 15
1
+Vcc
100nF
DALC 208
T1/E1 protection
USB port protection
VBUS D+ D-
Tx
SMP75-8 +Vcc 100nF DALC 208
GND 15k 15k
USB TRANSCEIVER
(1) Full speed only (2) Low speed only
DATA TRANSCEIVER
VBUS
+V 100nF
DALC 208
1.5k (1)
+V 1.5k (2)
Rx
SMP75-8
D+ DGND
USB TRANSCEIVER
Another way to connect the DALC208SC6
I/O2 I/O1
DALC208
I/O3
GND
I/O4
Note It's absolutely necessary to connect the pin 5 (REF1) to GND !
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DALC208SC6
PSPICE MODEL Fig. A11: PSpice model of one DALC208SC6 cell.
Vref2 0.8nH 0.3 Dpos 0.8nH 0.3 I/O
20 Current (A) / Voltage (V) 60 50 40 30 Current Surge I/O Voltage
Fig. A13a: PSpice model simulation: surge > 0 IEC 1000-4-2 contact discharge response.
Dneg 0.5 1.45nH Vref1
10 0 0 50 t(ns) 100
Fig. A13b: PSpice model simulation: surge < 0 IEC 1000-4-2 contact discharge response.
Current (A) / Voltage (V) 0 -10 -20 Current Surge I/O Voltage
Figure A11 shows the PSpice model of one DALC208SC6 cell. In this model, the diodes are defined by the PSpice parameters given in table below (Fig A12). Fig. A12: PSpice parameters. DPOS BV CJO IBV IKF IS ISR M N NR RS VJ 9 7p 1u 28.357E-3 118.78E-15 100E-12 0.3333 1.3334 2 0.68377 0.6 9 7p 1u 1000 5.6524E-9 472.3E-9 0.3333 2.413 2 0.71677 0.6 DNEG
-30 -40 -50
0
50 t(ns)
100
Fig. A14: Attenuation comparison.
dBm 0 Measured PSpice -10
Note: This simulation model is available only for an ambient temperature of 27C.
-20
The simulations done (Fig. A13, A14, A15) shows that the PSpice model is close to the product behavior.
-30
1
10 f(MHz)
100
1,000
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DALC208SC6
MARKING Type DALC208SC6 PACKAGE MECHANICAL DATA SOT23-6L (Plastic)
A
Marking DALC
Order Code DALC208SC6
Packaging (Base Qty) tape & reel (3000)
DIMENSIONS REF. A Millimeters Min. 0.90 0 0.90 0.35 0.09 2.80 1.50 0.95 2.60 0.10 3.00 0.60 10 0.102 0.004 Typ. Max. 1.45 0.15 1.30 0.20 3.00 1.75 Min. 0.035 0 0.035 0.004 0.11 0.059 0.0374 0.118 0.024 10 Inches Typ. Max. 0.057 0.006 0.0512 0.02 0.008 0.118 0.0689
H
A2
e
D
A1
b
A2 b C
A1
e
0.50 0.0137
D E e H
L
c M
E
L M
FOOTPRINT DIMENSIONS (in millimeters)
0.65 0.025
1.3 0.051 3.6 0.137 1 0.040
mm inch
0.95 0.037
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All rights reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com 10/10

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